The invention relates to semiconductor technology, and more specifically to carbon nanotubes (CNTs) applied in semiconductor interconnection.
As semiconductor device circuit density increases and device feature size decreases, increased numbers of patterned metal levels are required with decreased spacing between metal lines at each level to effectively interconnect discrete devices on semiconductor chips. Layers of insulating materials or films, typically referred to as inter-layer dielectric (ILD) layers, separate different levels of interconnections. Recently, copper lines and low-k dielectric have been utilized in the interconnections to reduce RC delay times and internal resistance. A low-k dielectric layer is formed on a substrate, followed by patterning to form damascene openings, and copper is filled in the damascene openings to form one of the wiring layers of the interconnections, copper being preferred for its resistance to chemical etching. The damascene openings are often incompletely filled when copper line width is reduced to 100 nm or less, increasing internal resistance of the interconnections or causing open circuitry, negatively affecting device reliability and process yield.
In other cases, low-k dielectric layers are often contaminated or damaged, resulting in increased dielectric constant. Thus, contaminated or damaged low-k dielectric layers are no longer “low-k” dielectric layers, negatively affecting the performance of the circuit, e.g., the frequency response or the like.